Interrupts
There are two sets of interrupts, CLINT (Timer and software interrupts) are described in the CLINT specification.
This chapter describes the platform interrupts.
The platform interrupts are generated from the following endpoints
- MRAM Interrupt: Raised by MRAM on ECC failure, to trigger a wellness check
- GPIO Interrupt: Raised by the GPIO module when any of the input signal changes state.
- Register Interrupt: A specific bit in the system register that can be written to to trigger an interrupt,e.g. this can be used by xSPI to interrupt the CPU and process the mailbox.
- Periph Interrupt: These interrupts are generated by QSPI,UART, I2C and xSPI Hardware to indicate state changes like TxDone, RxDone, FIFO under/over flow etc.
CPU Handling of platform interrupts
System interrupts are handled by the CPU subsystem PLIC which implements the RISCV PLIC 1.0 specification. The implementation details are: * The PLIC gateway assumes the connected interrupt sources are level-signals and they are synchronized to the CPU clock domain. * Interrupts priorities are not configurable: * Priorities registers are hardwire to 1 * Threadhold registers are hardwire to 0 * From the CPU point of view, PLIC base address is 0xA0000000 * Supports 32 contexts (2 contexts per hart, one M-mode and one S-mode).
The following table descrives the IDs for each interrupt source.
| Interrupt | ID |
|---|---|
| Reserved | 0 |
| MRAM interrupt | 1 |
| QSPI | 2 |
| UART | 3 |
| System Register | 4 |
| xSPI | 5 |
| GPIO | 6 |
Interrupt handling process.
This is a short overview. Refer to the RISCV privileged ISA for details
- A interrupt from a peripheral sets the corresponding bit in the corresponding Interrupt Pending register
- This is ANDed with the per-context (hart+priv mode) enable bits and forwarded to the context
- If the context have external interrupts enable, it will trap to their handler and read their Claim register
- The PLIC will respond with the enabled interrupt with the lowest id that is pending and mark it as claimed.
- Multiple harts can try to claim the same interrupt. Only one will get the id as a response.
- The hart that claimed the interrupt will handle it. After this process, the level-signal from the interrupt source must go low.
- The hart will mark the interrupt as completed by writing into the Claim register. This will free up the interrupt and can be claimed again if the pending bit is set.